1. Field of Invention
The present invention relates to the memory control circuit of a computer system. More particularly, the present invention relates to a feedback system on a computer motherboard capable of accommodating different memory module loading through delay adjustment.
2. Description of Related Art
Through rapid advance in semiconductor fabrication technologies, raw processing power of the central processing unit (CPU) inside a computer has increased considerably. Because of such rapid progress, clocking frequency of most personal computer (PC) has also increased from a few MHz in the past to more than one GHz now. To operate a high-power computer system, considerably amount of memory must also be used. Nowadays, most personal computer may contain several megabytes to a few gigabytes of memory. Following the increase in the clocking rate of CPU, most memory unit operates at a clocking frequency of 100 Mz or above.
A conventional low-speed memory control circuit transmits data by matching data signals with clocking signals. However, as the operating frequency of a computer system increases, such a simple arrangement is impossible to transmit data with sufficient accuracy. To increase data transmission capacity and improve high-speed transmission accuracy of memory signal, a data strobe (DS) method is introduced to reduce data loss due to high-speed transmission.
In some actual applications, data signal DAT and data strobe signal DS are transmitted synchronously from the same transmitting end. At the receiving end, the data strobe signal DS is delayed by a short interval. The short delay allows an integrated circuit to setup and hold a particular data signal such that the data can be accurately read. In other words, the transmitting end sends out a data signal DAT and a data strobe signal DS at the same edge of a clocking signal. Utilizing the almost identical delay trace of an integrated circuit, transmission route and integrated circuit buffer delays are balanced so that any skew between the data signal DAT and the data strobe signal DS is minimized.
In practice, the delay depends on a number of factors including the skew between the data signal DAT and the data strobe signal DS, the design of delay elements, the operating frequency of system and a few other environmental factors. Due to such complications, another method is suggested to tackle the delay setup problem. The method is to delay the data strobe signal DS by a quarter cycle of the clocking signal CLK. No matter what the clocking frequency of a particular system is, the data strobe signal DS always starts in the mid-portion of the positive half cycle or the negative half cycle of the a clock cycle CLK. By this means, accuracy of the data is ensured.
To ensure the triggering of the data strobe signal DS at a proper time, for example, at one quarter cycle delay of the clock signal CLK, and match the data signal DAT, most data strobe signal DS line includes a feedback route that connects from a half-way point to the memory unit to a data strobe feedback (DSF) pin. By tapping the return signal at the data strobe feedback (DSF) pin, status of signal transmission can be monitored and the moment to emit data strobe signal for obtaining correct data can be determined. In general, a phase lock circuit is employed to perform the timing adjustment.
FIG. 1 is a sketch of a conventional feedback control circuit of a memory module. As shown in FIG. 1, the control chipset 10 has a plurality of data strobe pins DQS[0:8] and a data strobe feedback pin DQSFB. The data strobe pins DQS[0:8] are connected to the data strobe pins (not shown) of a plurality of memory module slots 12, 14 and 16. A trace line is selected such that a branch back line is tapped at a halfway point back to the data strobe feedback pin DQSFB. The branching point is set to make the path length from the point to the memory module slots 12, 14, 16 (Path 1) and the path length from the point to the data strobe feedback pin (Path 2) almost identical. Hence, almost identical transmission delay is simulated. With this arrangement, signal submitted to the data strobe feedback pin DQSFB of the control chipset reflects actual data strobe delay at the memory module terminal.
However, actual delay is also dependent upon the loading at the memory module slots. In other words, the data transmission delay varies according to the number of memory modules plugged into the memory module slots and the number of integrated circuits inside the memory module. The aforementioned feedback system has no special mechanism for adjusting the timing between data signal DAT and data strobe signal DS according to the actual memory module loading. Therefore, the stability of a computer system may be affected.
In addition, signal waveform arriving at the memory slot terminal is slightly distorted due to the presence of a branch along the trace line. Such distortion is likely to affect timing tolerance when data are read. Moreover, the conventional feedback system demands setting of the branching point to a position where the path length from the point to the memory module slot and the path from the point to the data strobe feedback pin are identical. Hence, wiring layout is further constrained and additional printed circuit board area may be required.
Accordingly, one object of the present invention is to provide a feedback system capable of accommodating different memory module loading. In other words, the feedback system can self-adjust to accommodate any number of memory modules plugged into the memory slots and any difference in the number of integrated circuits inside the memory module. Consequently, the control chipset is able to adjust the timing between the data signal DAT and the data strobe signal DS according to the actual memory loading so that data transmission accuracy is greatly improved.
A second object of the invention is to provide a feedback system capable of accommodating different memory module loading without having to set a branching point in such a way that the path from the point to a memory module slot and the path from the point to a data strobe feedback pin are almost identical. Hence, layout design is simplified and demands for printed circuit board area is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a feedback system in a computer system for accommodating different memory module loading. The feedback system includes a plurality of memory module slots, a control chipset, a variable reference voltage and a comparator. The memory module slots can accommodate at least one memory module. The control chipset has a plurality of data strobe pins and a data strobe feedback pin. The data strobe pins are connected to the data strobe pin on the memory module slots. The variable reference voltage provides a reference voltage. The comparator has a first input terminal, a second input terminal and an output terminal. The output terminal of the comparator is connected to the data strobe feedback signal pin. The first input terminal of the comparator receives a reference voltage. The second input terminal of the comparator is connected to any point along the line from the data strobe pins of the control chipset to the data strobe pins at the memory module slots. The variable reference voltage is set by the computer system so that output timing of the comparator can be adjusted. Through the adjustment of the reference voltage, a suitable data strobe feedback signal is sent to the control chipset for adjusting data signal DAT and data strobe signal DS timing and obtaining accurate data from the memory module.
According to one embodiment of this invention, the variable reference voltage of the feedback system is under the control of a control signal. The control signal is issued from the control chipset. When a computer system is started, the computer system will automatically read out the state of assembly of the memory modules plugged onto the memory module slots. The variable reference voltage is set according to the state of assembly. However, a user may set up some other configuration through the basic input/output system of the computer.
The invention provides a second feedback system in a computer system capable of accommodating different memory module loading. The computer system uses memory modules. Each memory module has loading pins and simulating loads. The simulating loads are connected to the loading pins. The feedback system of this invention includes a plurality of memory module slots and a control chipset. Each memory module slot can accommodate a memory module and has a loading pin. When a memory module is plugged into the memory module slot, the loading pin on the memory module is connected to the loading pin of the memory module slot. The control chipset is coupled to the memory module slots. The control chipset has data strobe pin and data strobe feedback signal pin. The data strobe pins of the control chipset are first connected to the loading pins of any one of the memory module slots and then serially connected to the other memory module slots. The last memory slot is connected to the data strobe feedback signal pin to form a xe2x80x98branchlessxe2x80x99 signal feedback loop. When a memory module is plugged into the memory slot, the control chipset utilizes the signal received from the data strobe feedback pin to simulate the delay caused by the load on the memory slot. Hence, data can be accurately written to or read from the memory module.
The invention provides a third feedback system capable of accommodating different memory module loading. The feedback system includes a plurality of memory module slots and a control chipset. The memory module slots can accommodate at least one memory module. Each memory slot has data strobe pins. The control chipset is coupled to the memory slots. The control chipset has data strobe pins and a data strobe feedback pin. The data strobe pin of the control chipset is first connected to the data strobe pin of any one of the memory slots and then serially connected to the data strobe pin of the other memory slots. The last memory slot is connected to the data strobe feedback pin of the control chipset to form a xe2x80x98branchlessxe2x80x99 signal feedback loop. When a memory module is plugged into the memory slot, the control chipset utilizes the signal received from the data strobe feedback pin to obtain loading information on the memory slot. Hence, the delay can be computed and data can be accurately written to or read from the memory module.
The invention provides a fourth feedback system capable of accommodating different memory module loading. The feedback system includes a plurality of memory module slots, a plurality of simulating loads, a group of switches and a control chipset. The memory slots can accommodate at least one memory module. The simulating loads are used to simulate the delay caused by memory module loading. The switches are coupled to the simulating loads for activating a portion of the simulating loads. The control chipset is coupled to the memory slots. The control chipset has data strobe pins and a data strobe feedback pin. The data strobe pins of the control chipset are first connected to the simulating loads and then connected back to the data strobe feedback pin. When a memory module is plugged into the memory slot, the switches activate a portion of the simulating loads. The control chipset utilizes the signals received from the data strobe feedback pin to simulate possible delay caused by the loading condition at the memory slot. Hence, data can be accurately written to or read from the memory module.
According to another embodiment of this invention, the group of switches for activating the simulating load is triggered by a switch control signal. The switch control signal is issued by the control chipset. After the computer system is switched on, the computer system will automatically read out information about the state of assembly of memory modules in the memory slots. According to the configuration information, the group of switches is set to activate a portion of the simulating load simulating the actual loading condition of the memory modules. Alternatively, a user may set the grouping state of the memory module and hence the switches by programming through the basic input/output system.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.